Posted Aug 16

Nvidia is hiring a
DFT Engineer

India, Hyderabad
Full time

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work, to amplify human imagination and intelligence. Make the choice to join us today. NVIDIA is an equal opportunity employer.

Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips.

What you'll be doing:

  • As a member of our team, you will be leading the design and implementation of state-of-the-art designs in test access mechanisms, ATPG, BIST and compression.

  • Your responsibility will also include verification and silicon bring-up of Scan ATPG and other DFT features. We are looking for innovation to improve the quality of DFT methods which includes DFT clocking, pattern reduction and coverage improvement.

  • In addition, you will help develop and deploy DFT methodologies for our next generation products. You will also need to work with multi-functional teams to incorporate DFT features into the chip. Occasional travel and some late hours online meetings involved during critical design phase.

What we need to see:

  • BSEE or MSEE or equivalent experience from reputed institutions with 3+ years of industrial experience.

  • Strong DFT knowledge in Scan ATPG, compression techniques. Experience in coverage analysis, test points and DFT clocking is desired. Candidate should be well versed with DFT static timing analysis, ECO, ASIC Design Flow, HDL and Digital logic design. Experience in RTL and Gates verification and simulation. Tape-out experience gives added advantage.

  • You need to be familiar with BIST architecture and JTAG/IEEE1149.1/IEEE1500.

  • Strong analytical, problem-solving skills and strong coding skills in industry standard scripting languages. Outstanding written and oral communication skills with the curiosity to work on rare challenges.

Please mention that you found the job on ARVR OK. Thanks.