Samsung Research America is hiring a
Lead SoC Architect, NPU AI/ML

Lab Overview:

The Samsung SOC Lab vision provides innovative SoC architecture, bus / memory subsystem, multimedia subsystems and key IP blocks for future Samsung Galaxy products (Smartphones, tablets and future devices). We are defining the high performance SoC architecture development for various Galaxy device lineups. This lab collaborates with Samsung's strategic SoC partners, Samsung MX headquarter team, and key R&D teams around the globe to innovate and reinvent technology that will positively impact millions of people around the world via the Galaxy flagship products.

Position Summary:

We are looking for a Lead SOC Architect, NPU for next generation SOCs. This is a highly visible hands on role leading individual and team contributions to NPU [AI/ML] sub-system architecture, interface, performance and power tradeoffs.

Position Responsibilities:

• Guide on development of innovative NPU Architectural and microarchitectural features to boost PPA (Performance, Power and Area) on various targeted workloads in next generation SOCs.
• Identify and deliver NPU subsystem architecture proposals for products in new and existing markets.
• Good knowledge of existing AI/ML algorithms usage in Smartphone, AR/VR/XR applications.
• Evaluate architecture proposal benefits in collaboration with team of SoC Architects and communicate the results across related engineering audiences (SW, HW, Architecture, Leadership).
• Perform high-level performance modeling/simulation and analysis of NPU features, applications, benchmarks, and complex uses cases.
• Direct, Work hands-on and orchestrate performance modeling, and studies to support inclusion of these features in the next generation SoC.
• Deliver architecture/microarchitecture proposals and specifications to the design team and articulate them effectively across audiences ranging from hardware & software engineers to architecture community peers, and to technology leadership.
• Collaborate with silicon and platform bring-up and product teams to verify and debug the proposal and its delivered performance.
• Collaborate across teams to bring microarchitectural proposals to fruition across the SOC, Driver, OS, System through detailed documentations.

Required Skills:

• BSc, Masters, or PhD in Computer Science/Engineering, or equivalent combination of education, training, and experience.
• 15+ years of experience in SOC or ASIC design and architecture.
• Prior direct experience (> 7 years) in NPU subsystem architecture or microarchitecture is required.
• High proficiency in architecture analysis and performance modeling, ranging from simple analytical models to complex cycle accurate performance model and correlation, especially around NPU IPs.
• Ability to leverage existing simulation capabilities [GEM5, FastSIM, Platform Architect] or create new simulation capabilities when necessary.
• Detailed knowledge of ARM bus infrastructure (ACE/AXI/AHB), GPU architecture and new development.
• Leadership across hardware, software, and platform groups to align all parties to a common vision.