Posted Aug 16

Nvidia is hiring a
Senior ASIC Design and PPA Efficiency Engineer

US, CA, Santa Clara • 3 Locations • 3 Locations
Full time

NVIDIA is seeking an outstanding Senior ASIC Design Engineer to design and implement the world’s leading SoC's and GPU's. This position offers the opportunity to have a real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of extraordinary people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.

What you’ll be doing:

  • As a key member of our design team, you will be responsible for the micro-architecture and design implementation of GPU memory subsystem/interconnects modules.

  • Identify inefficiencies and improvement opportunities in the front-end chip implementation process and develop methodology and infrastructure to drive Performance, Power and Area (PPA) improvements

  • Define and develop system-level methodologies and tools to build interconnects in an efficient and scalable manner

  • Deliver a synthesis/timing clean design while working with the physical design team to ensure a routable and physically implementable design.

  • Collaborate with architects, verification engineers, software engineers, and physical design engineers to accomplish your goals.

What we need to see:

  • Bachelors or Masters Degree in Electrical Engineering or Computer Engineering, or equivalent experience.

  • At least 5 years of relevant work or research experience.

  • Highly proficient in logic design, Verilog and/or System-Verilog, with a good understanding of Computer Architecture and Digital Systems design.

  • A deep understanding of ASIC design flow including RTL design, verification, logic synthesis, timing analysis, floor-planning, System-On-Chip design/integration flow, and design automation.

  • Strong coding skills in Perl, Python, or other industry-standard scripting languages.

  • Great communication and teamwork skills to interact within the team and across functional teams to build consensus.

Ways you can stand out from the crowd:

  • Prior design experience with arbiters, scheduling, synchronization, bus protocols, interconnect networks and/or caches.

  • Familiarity with memory subsystem concepts such as memory management, cache consistency model, arbitration policies, high-speed IO protocols and/or on-chip interconnect.

  • Good debugging and analytical skills.

NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and dedicated people in the world working for us. Are you creative and autonomous? Do you love the challenge of crafting the highest performance & lowest power silicon possible? If so, we want to hear from you. Come, join our GPU ASIC team and help build the real-time, cost-effective computing platform driving our success in this exciting and quickly growing field.

The base salary range is $124,000 - $247,250. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

You will also be eligible for equity and benefits.

NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

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