Nvidia is hiring a
Senior ASIC Design Engineer

NVIDIA is hiring a  Senior  ASIC Design / RTL Engineer to design, analyze, and evolve next generation SoC solutions. We are looking for special individuals with passion and desire to deliver innovative products. Together, we will build the next generation of life changing SoC's. If you are a motivated individual that understands how SoC systems are architected and built, has intimate knowledge of client requirements, and understand various development cycles, this is your place to be 

What you'll be doing: 

• Work with Architects, Chip Leads, and Customers on SOC IP design, development, timing closure, power analysis, methodology alignment, and program execution to ensure pre-silicon and post silicon targets are met. 

• Integrating, evolving, and optimizing IP blocks across a range of products and use cases for NVIDIA SoCs in driving, 5G, cloud and gaming and other applications. 

• Working with teams throughout the company (Architects, RTL, PD, Circuit, SI, Thermal, SW, Platform, Operations, Marketing, etc...) on implementing cross-team solutions to achieve project targets. 

• Working with customers, partners, and IP vendors to understand IP solutions best suited for our target use cases and work with them to select and integrate appropriate IP solutions. 

• Drive cross team methodologies for RTL development and microarchitecture. 

What we need to see: 

• Master's Degree in Computer Engineering or Electrical Engineering (or equivalent experience).

• 10+ years of relevant work experience in RTL development focused on CPU, GPU, and high performance architectures. 

• Proficiency in industry standard RTL development and synthesis tools. 

• Experience developing high speed digital blocks. 

• Experience debugging complex microarchitectural structures 

• Strong interpersonal, communication and teamwork skills. 

• A drive to continuously learn and expand architectural breadth and depth. 

• Ability to evaluate microarchitectural options for tradeoffs across design, verification, and PD. 

• Experience interconnecting and analyzing complex microarchitectural structures and subsystems.