Nvidia is hiring a
Senior ASIC Verification Engineer, Coherent High Speed Interconnect
We are now looking for a ASIC Verification Engineer - Coherent High Speed Interconnect! For two decades, we have pioneered visual computing, the art and science of computer graphics. With our invention of the GPU - the engine of modern visual computing - the field has grown to encompass video games, movie production, product design, medical diagnosis, and scientific research.
Today, we stand at the beginning of the next era, the AI computing era, ignited by a new computing model, GPU deep learning. This new model - where deep neural networks are trained to recognize patterns from massive amounts of data - has shown to be deeply effective at solving the most complex problems in everyday life. As a ASIC Verification Engineer at NVIDIA, you will verify the design and implementation of our innovative high speed coherent interconnects for our mobile SoCs and GPUs. This position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.
What you'll be doing:
Responsible for verification of high-speed coherent interconnect design, architecture, golden models, and micro-architecture using sophisticated verification methodologies.
You'll understand the design & implementation, define the verification scope, develop the verification infrastructure (Testbenches, BFMs, Checkers, Monitors), complete test/coverage plans, and verify the correctness of the design.
Collaborate with architects, designers, emulation, and silicon verification teams to accomplish your tasks.
What we need to see:
Bachelors or Master’s Degree (or equivalent experience) ; 5+ years of relevant verification experience.
Experience in architecting test bench environments for unit level verification.
Background in verification using random stimulus along with functional coverage and assertion-based verification methodologies. Prior Design or Verification experience of Coherent high-speed interconnects.
Knowledge of industry standard interconnect protocols like PCIE, CXL, CHI will be useful.
Strong background developing TB's from scratch using SV and UVM methodology is desired.
C++ programming language experience, scripting ability and an expertise in System Verilog.
Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB).
Strong debugging and analytical skills. Experienced communication and interpersonal skills are required. A history of mentoring junior engineers and interns a huge plus.
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