Nvidia is hiring a
Senior Custom SOC IP Verification Engineer
NVIDIA is seeking a Senior Custom SOC/IP Verification Engineer to verify the next generation SoC and IP solutions. We are looking for special individuals with passion and desire to deliver innovative products. Together, we will build the next generation of life changing custom SOCs. If you are a motivated individual that understands how complex SOC and IPs are built, and understand various development cycles, this is your place to be.
What you'll be doing:
Responsible for ASIC design verification for various IPs at IP and SOC levels
Participate in IP/SOC architecture, micro-architecture reviews, interface with Architecture, SW/FW, Design, and Modeling to ensure comprehensive first-time right verification plans
Work on the innovative verification methodology development, functional and code coverage closure
Contribute to the development of silicon and platform verification strategy and methodology
Collaborate with IP development teams, and participate in, and support soft and hard IP identification, selection, and IP licensing
Assist in interviews, training newcomers
What We Need To See:
Clear understanding of complexities involved with various design verification tools, including Synopsys VCS or Cadence Xcelium Simulator, Verdi, JasperGold or VC Formal
Track record of first-pass success in ASIC Development
B.S. or M.S. degree in Computer Engineering or Electrical Engineering
Experience working across multiple projects and adjusting priorities in partnership with stakeholders
5+ years of experience owning processing ASIC, IP or SoC design verification
Experience managing and delivering complex mixed language UVM and C++ testbenches
Ability to interpret functional specs and creating comprehensive test plans
Ability to write directed and constraint random test to achieve coverage-driven verification closure
Experience developing tools and infrastructure using Perl or Python
Ways to stand out from the crowd:
Strong background with AMBA protocols such as AXI, ACE, CHI, ATB, etc.
Hands-on experience with complex subsystems in new technologies like ARM CPU complex, LPDDR, HBM, GPU’s, DLA, PCIE or Network on chip and with performance verification
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