Nvidia is hiring a
Senior Physical Design Engineer
NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work, to amplify human imagination and intelligence. Make the choice to join our dynamic team today!
We are actively looking for Physical design Engineers with RTL2GDS experience to implement complex high performance and low power SOC’s.
What you'll be doing:
Responsible to Floor Planning and Place and route (P&R) of High-performance chip partitions.
Integration on Analog IO’s and macros.
Work on power grid planning, Clock tree Synthesis (CTS) and timing closure.
Multi mode and multi corner timing closure, RC extraction, Cross talk, IR drop and EM analysis.
Work with the Front-end teams to update and tune timing constraints.
Debugging timing violations and rolling in functional, Timing ECO’s and netlist formal verification.
Physical verification- ERC, DRC, LVS etc.
What we need to see:
Bachelor's or a Master’s degree in Engineering (or equivalent experience)
5+ years of hands-on experience in Physical design.
Place and route tool experience with Synopsys ICC2 or Cadence Innovus
Static timing analysis with Synopsys Primetime.
Understanding of DFT and multi-mode timing analysis.
Ability to automate flows.
You will also be eligible for equity and benefits.
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