Nvidia is hiring a
Senior SOC Design Engineer
We are looking for a Senior SOC Design Engineer. The complexity of the chips we build has increased manifold over the years. We are now packing tens of billions of transistors in a chip to meet the growing computing demand. The NVIDIA System-On-Chip (SOC) group is looking for a star candidate with an interest in RTL integration and chip level front-end design, including padring, pinmuxing, SOC Assembly process, and fuse / floor-sweep design. You must have a real passion for methodologies and automation solutions that enable SOC creation in the most optimized way.
In this position, you will get the chance to build complex Tegra SOCs, work closely with chip management to set ASIC execution timelines & goals while interfacing directly with System Architecture, unit-level ASIC, Physical Design, CAD, Package Design, DFT and other teams. Additionally, you will be involved in defining and creating methodologies that create more efficient and flexible SOCs in future.
What you'll be doing:
Drive SOC Assembly/Integration and design chip level functions for Tegra SOCs.
Responsible for front-end design quality/correctness checks, reviews and driving those with cross-functional teams.
Drive SOC execution across chip milestones working with all cross-functional teams to help define, track and drive complex dependencies.
Define and develop system-level methodologies, tools, and IPs to build SOCs in an efficient and scalable manner.
Identify pain points and inefficiencies in the front-end chip implementation process and propose ideas to solve them.
What we need to see:
B.Tech or M.Tech or equivalent experience in Electronics or Computer Engineering.
5+ years of industry experience in chip design, specializing in SOC integration and design automation. Padring and fuse / floorsweep design experience is a plus.
Excellent analytical and problem-solving skills.
Experience in RTL design (Verilog), System-On-Chip design/implementation flow, and design automation.
Strong coding skills in Perl, Python, or other industry-standard scripting languages.
Exposure to various Chip Design Functions to be able to collaborate and solve complex cross functional problems.
Excellent communication skills to interact with cross functional teams to build consensus.
Good teamwork spirit and collaboration skills with team members.
Experience in synthesis, physical design and DFT s a plus.
Experience in RTL Build and Design Automation is a plus.
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