Nvidia is hiring a
Senior Verification Engineer
NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can take on, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. Make the choice to join us today.
We are now looking for a Senior Verification Engineer to join this dynamic and innovative team. Design-for-Test (DFT) Engineering at NVIDIA works on groundbreaking innovations every single day. We craft creative solutions for DFT architecture, implementation, verification and post-silicon validation on some of the industry's most complex semiconductor chips. We use the best industry tools and go beyond with internal methodologies to take on some of Nvidia's unique challenges. We are looking for you to implement the best ASIC verification methodologies for DFT IP at unit and system levels. You will bring in expertise in SystemVerilog, UVM, FPGA, Emulation and own their application in DFT domain.
What you'll be doing:
Build "state of the art" verification test benches and methodologies to verify DFT features in complex IP's/Sub-systems/SOC's.
Develop and own verification environment using SVTB/UVM.
Build reusable bus functional models, monitors, checkers and scoreboards.
Own functional coverage driven verification closure and own design verification sign-offs at multiple levels.
Interact closely with multi-functional teams like chip architecture, ASIC design, functional verification, and post silicon teams.
Strive to improve the quality of DFT methods
What we need to see:
BSEE (or equivalent experience) with 5+ or MSEE with 3+ years of experience in design verification or related domains
Expertise in System Verilog and verification methodologies like SVTB/UVM.
Expertise in prototyping, verification and debug tools (Emulation, FPGA, VCS, Debussy, Formality, PrimeTime etc).
Good exposure to ASIC design methodologies: RTL design, clocking, timing and low-power architectures.
Strong programming/scripting skills in C++, Perl, Python or Tcl
Excellent written and oral communication skills
Strong analytical skills
Ways to stand out from the crowd:
Strong experience in both RTL and Gates Verification domains
Knowledge in Formal verification methodologies and tools for IP and SoC level verification
Hands-on experience in post silicon debug on ATE and/or system labs.
You will also be eligible for equity and benefits.
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